statistiche ricercatore

Continente	#
NA - Nord America	1.915
EU - Europa	917
AS - Asia	596
SA - Sud America	149
AF - Africa	19
Continente sconosciuto - Info sul continente non disponibili	1
Totale	3.597

Nazione	#
US - Stati Uniti d'America	1.867
SG - Singapore	268
IT - Italia	240
RU - Federazione Russa	233
CN - Cina	164
GB - Regno Unito	130
BR - Brasile	122
DE - Germania	89
VN - Vietnam	62
UA - Ucraina	36
CA - Canada	31
IE - Irlanda	29
ES - Italia	21
FI - Finlandia	20
SE - Svezia	20
FR - Francia	18
HK - Hong Kong	18
AR - Argentina	17
NL - Olanda	17
AT - Austria	16
JP - Giappone	14
MX - Messico	14
PL - Polonia	12
BD - Bangladesh	11
IN - India	11
DK - Danimarca	9
IL - Israele	9
ZA - Sudafrica	9
ID - Indonesia	8
PK - Pakistan	6
PT - Portogallo	6
BE - Belgio	5
EC - Ecuador	5
TW - Taiwan	5
CZ - Repubblica Ceca	4
IQ - Iraq	4
AL - Albania	3
CH - Svizzera	3
TR - Turchia	3
CL - Cile	2
EG - Egitto	2
IR - Iran	2
JO - Giordania	2
KE - Kenya	2
KR - Corea	2
MA - Marocco	2
AE - Emirati Arabi Uniti	1
BY - Bielorussia	1
CO - Colombia	1
DZ - Algeria	1
EE - Estonia	1
ET - Etiopia	1
EU - Europa	1
GD - Grenada	1
GN - Guinea	1
GR - Grecia	1
HN - Honduras	1
KG - Kirghizistan	1
KZ - Kazakistan	1
LB - Libano	1
LT - Lituania	1
PH - Filippine	1
PY - Paraguay	1
RS - Serbia	1
SA - Arabia Saudita	1
SK - Slovacchia (Repubblica Slovacca)	1
TN - Tunisia	1
TT - Trinidad e Tobago	1
UZ - Uzbekistan	1
VE - Venezuela	1
Totale	3.597

Nome	#
A Framework for Supporting Real-Time Applications on Dynamic Reconfigurable FPGAs	468
ARTE: Arduino real-time extension for programming multitasking applications	451
A bandwidth reservation mechanism for axi-based hardware accelerators on FPGAs	426
A Linux-based support for developing real-time applications on heterogeneous platforms with dynamic FPGA reconfiguration	362
A Linux-based support for developing real-time applications on heterogeneous platforms with dynamic FPGA reconfiguration	327
ARTe: Providing real-time multitasking to Arduino	311
Is your bus arbiter really fair? Restoring fairness in axi interconnects for FPGA SOCs	303
Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC	301
Bounding Memory Access Times in Multi-Accelerator Architectures on FPGA SoCs	244
Spatio-Temporal Optimization of Deep Neural Networks for Reconfigurable FPGA SoCs	229
Modeling and analysis of bus contention for hardware accelerators in FPGA SoCs	198
Totale	3.620

	Totale	Lug	Ago	Sett	Ott	Nov	Dic	Gen	Feb	Mar	Apr	Mag	Giu
2020/2021	154	0	0	0	0	0	31	17	10	11	14	36	35
2021/2022	203	15	19	7	12	4	17	20	26	9	24	27	23
2022/2023	211	15	22	23	41	18	25	2	9	25	11	8	12
2023/2024	186	9	2	24	11	4	35	7	11	19	24	12	28
2024/2025	727	38	18	37	15	35	50	121	180	55	19	112	47
2025/2026	1.784	101	269	871	285	201	57	0	0	0	0	0	0
Totale													3.620